The present invention relates to a differential type MOS transmission circuit, more particularly to techniques useful specifically when used for signal transmission between LSIs on a circuit board for a digital processing device constructed mainly by using CMOS or bipolar.CMOS (BiCMOS) circuits.
By constructing a digital processing device mainly by using CMOS or BiCMOS circuits it is possible to achieve high speed performance, high density integration and low electric power consumption. In such a digital processing device, if signals transmitted between LSIs (semiconductor integrated circuits) mounted on a circuit board have relatively large signal amplitudes of MOS level such as e.g. 5 V, because of the relatively large signal amplitudes, when the number of transmitted signals or the length of transmission lines between different circuit boards or LSIs is increased with increasing scale of the digital processing device, high speed operation in the whole digital processing device is hindered and further electric power consumption is increased. That is, the signal transmission method in the digital processing device is an important factor dominating performance of a system.
Therefore the inventors of the present application have developed a signal transmission method for transmission lengths not more than 10 m prior to the present invention. The content thereof is disclosed in JP-A-2-143609 published on Jun. 1, 1990 and in an article "Conference No. ICD92-27 (June 1992)" Kumamoto Meeting 1992 of Study Group on Integrated Circuit, Electronic Information Communication Society. That is, in order to realize low electric power consumption and high speed transmission, transmission of low amplitude signals, e.g. signals having an amplitude of about 300 mV, utilizing differential signals is adopted by this method, by which a series resistance is inserted into a differential signal output terminal of relevant TTL level of an LSI having an output signal amplitude of TTL level, e.g. 0 V.about.3 V, so as to decrease the amplitude of the differential output signal of relevant TTL level by resistance voltage dividing with an impedance ratio determined by the series resistance and a terminal resistance. The differential signal having an amplitude reduced in this way is supplied to another LSI receiving circuit through a pair cable. The first stage of this receiving circuit serves both as a level shift circuit and as a preamplifier in common. The output of this first stage is amplified by a main amplifier to be supplied to an internal logic circuit in that LSI.
However it was revealed by the inventors of the present application that there is a problematical point as follows, in the case where high density integration or high density mounting of digital processing devices is advanced and signal transmission is effected by means of a number of transmission circuits described above. At first, operation speed of a driver on the transmitter side is inferior to requirement for a higher signal transmission speed. That is, although the signal amplitude on the pair cable is relatively reduced by resistance voltage dividing, since the amplitude of the output signal itself of the LSI is relatively high as the TTL level, the driver should perform output operation with a full swing of the amplitude of the output signal. For this reason there is a limit in increasing the speed of the output operation, i.e. the signal transmission speed. Secondly, since it is necessary to mount resistance elements on a circuit board for the resistance voltage dividing, the ratio of an area for mounting the relevant resistance elements on the circuit board to the whole surface of the circuit board increases, which lowers packaging efficiency of the circuit board.